1. Field of the Invention
The present invention relates to a method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe using the same method.
More particularly, the present invention relates to a method of manufacturing an enhancement type semiconductor probe using an anisotropic wet etching and a side-wall. In the method, influence of process parameters upon the performance of a device is reduced to improve reliability of the device in mass-production, and factors of degrading measuring sensitivity is removed to improve the performance of the device.
Further, the present invention relates to an information storage device having the enhancement type semiconductor probe using the same method.
2. Description of the Prior Art
Recently, ferroelectric materials have been used in many applications. To read-out information stored in the ferroelectric materials, various devices have been studied and developed. As compared to other detector devices, a resistant probe shows high sensitivity and resolution and is very convenient in utilization.
However, a presently used process of manufacturing a device has a high possibility of changing in device performance according to process parameters, and has a problem in that the performance of the probe is degraded below a level projected for the reason to be described later. Thus, as regards future development of a probe in consideration of commercialization thereof, it needs a process method having higher sensitivity and resolution and being lightly influenced by the process parameters.
Hereinafter, a related art method of manufacturing a semiconductor probe and problems thereof will now be explained in detail with reference to the accompanying drawings.
FIGS. 1A to 1J are sectional process views illustrating a related art method of manufacturing a semiconductor probe having a resistance tip.
First, as shown in FIG. 1A, a mask layer 13 such as a silicon oxide or a silicon nitride is formed on the surface of a silicon substrate 11 or a silicon on insulator (SOI) substrate, doped with first impurities, a photosensitive agent 15 is applied thereon, and a stripe type mask 18 is placed thereon.
Next, exposure, shaping and etching are performed to carry out patterning. Through the photolithography and etching, as shown in FIG. 1B, a stripe type mask layer 13a is formed on the substrate 11, and an area other than the mask layer 13a is highly doped with second impurities to form first and second semiconductor electrode regions 12 and 14.
Next, annealing is performed to reduce a width between the first and second semiconductor electrode regions 12 and 14 below a width of the mask layer 13a. As shown in FIG. 1C, when the heavily-doped regions 12 and 14 of the second impurities are enlarged, the second impurities are diffused into a region adjacent to the heavily-doped regions to form a lightly-doped region of the second impurities. That is, resistance regions 16 are formed. The resistance regions 16 under the mask layer 13a are in contact with each other to form a peak-formation portion of a resistance tip.
Next, a photosensitive agent 19 is applied onto the upper face of the substrate 11 to cover the mask layer 13a and, as shown in FIG. 1D, a stripe type photo mask 20 is placed thereon so as to be crossed at a right angle with the mask layer 13a. Then, the exposure, development and etching are performed to form a photosensitive layer 19a having the same type as the photo mask 20 (See FIG. 1E).
Next, the mask layer 13a that is not covered with the stripe type photosensitive layer 19a is dry-etched to form a rectangular mask layer 13b (See FIG. 1F).
Then, as shown in FIG. 1G, the photosensitive layer 19a is removed and the substrate 11 is wet or dry-etched using the rectangular mask layer 13b as a mask to thereby locate the first and second semiconductor electrode regions 12 and 14 on an inclined face of a tip 10 and to arrange the resistance regions 16 as a peak portion of a tip (See FIG. 1H).
Next, when the substrate 11 is annealed under an oxygen atmosphere after the mask layer 13b is removed, a silicon oxide (not shown) having a certain thickness is formed on the substrate 11. When the oxide is removed, the end point of the resistance regions 16 are sharpened. Then, through performing a thermal oxidation process, the isolated resistance regions 16 can be overlapped together with sharpening of the tip.
Next, as shown in FIG. 1I, a dielectric layer 30 is deposited on the substrate 11 to cover the resistance tip 10. Then, the dielectric layer 30 on the tip 10 is planarized by a chemical-mechanical polishing (CMP). A metal is deposited on the dielectric layer 30 to form a metal shield 32. Next, the metal is removed from a region facing against the resistance regions 16 through a patterning process to form an opening 33 having a certain size on the metal shield 32.
Next, as shown in FIG. 1J, the substrate 11 is etched on its lower face to form a cantilever 40 such that the resistance tip 10 is positioned at its distal end, and the first and second semiconductor electrode regions 12 and 14 are connected to an electrode pad 54 isolated by an insulating layer 52 on the substrate 11, thereby forming a semiconductor probe. Then, an electrode pad 64 for ground voltage is formed on the metal shield 32.
As described above, in the related art method of manufacturing the semiconductor probe having the resistance tip, a pyramid type probe is formed using a mask of a few μm and an isotropic wet etching. In this method, the device performance is greatly varied according to a change in a position and a size of the mask. That is, there are some process parameters in an attempt to make a sharp point of the probe at an exact position using a large mask. The related art method depending on the process parameters as such has a great limit on manufacturing and using a probe commercially. Thus, a factor in reliable manufacturing of a device may be the provision of a mask and an etching method which are comparatively free from the process parameters of the related art. In addition, to this end, a small mask is used from the beginning in manufacturing a device so as to reduce an error factor.
Table 1 below shows the simulation results of the probe sensitivities with respect to mask widths, with 4 μm being the desired mask width.
TABLE 1Mask Width4 μm4.02 μm4.1 μmSensitivity0.031%0.02%0.017%
In Table 1, it can be seen that even upon the occurrence of an error in the order of 0.5% from a size intended, the sensitivity is reduced by approximately 30%. The presence of the process parameter affecting the device performance as such places a great limit on the future commercialization of a device, so that such problem should be solved.
Beside the above problem, when the device sensitivity is lower than that intended it causes many possible problems because it results in degradation in performance and the like. It can be analyzed that a cause of such degradation in performance is because source/drain regions that are heavily doped in the process of wet etching are etched and remain as a lightly doped region, so that resistance of the source/drain regions having a large size hardly increases the total current by distribution of electric charges.
The above device can be modeled like in FIG. 2. The model includes resistance Rm, Rs, Rd, R1 and R2. In FIG. 2, since resistances Rs, Rd of the source/drain regions is very large, upon the connection of a voltage source to both ends thereof, variation in total current hardly occurs even upon the occurrence of variation in resistance Rm of the probe tip. In addition, since resistance Rm of the region practically detecting electric charges is much greater than R1 below, most of the current flows to the R1 region so that Rm has little influence on the total current. Thus, to achieve higher device sensitivity, it is required to make Rm much greater than R1 and to make resistances of the source/drain regions reduced.